module seqdec_22(InA,Clk,Reset,Out);

	input InA, Clk, Reset;
	output Out;
	wire d1,d2,d0;
	wire q1,q2,q0;
	wire q1bar,q2bar,q0bar, InAbar;
	wire tmp1,tmp2,tmp3,tmp4,tmp5;
	wire tmp6,tmp7,tmp8,tmp9,tmp10;
	wire tmp11,tmp12,tmp13,tmp14,tmp15;
	wire tmp16,tmp17,tmp18,tmp19,tmp20;

	not1 inst25(q0,q0bar);
	not1 inst26(q1,q1bar);
	not1 inst27(q2,q2bar);
	not1 inst28(InA,InAbar);
 /*       	
//assign d0 = ((~q0)&(~(q1^InA)))|(q2&q0&(q1^InA));
//second part of Y0
	xor2 inst1(q1,InA, tmp1);
	nand3 inst2(q2,q0,tmp1,tmp2);
//first part of Y0
	xor2 inst3(q1,InA,tmp3);
	not1 inst4(tmp3,tmp4);
	nand2 inst5(q0bar,tmp4,tmp5);
//Y0
	nand2 inst6(tmp2,tmp5,d0);
*/
//first part of Y0
	nand3 inst1(q1bar,q0bar,InAbar, tmp1);
//second part of Y0
	nand3 inst2(q1,q0bar,InA,tmp2);
//third part of Y0
	nor2 inst3(q1,q0bar,tmp3);
	nand3 inst4(q2,tmp3, InA, tmp4);
//Y0
	nand3 inst5(tmp1,tmp2,tmp4,d0);

//first part of Y1
	nand2 inst10(q1,q0bar,tmp9);
//second part of Y1
	nor2 inst11(q1,q0bar,tmp10);
	nand2 inst12(q2bar,InAbar, tmp11);
	nand2 inst13(q2bar,tmp11,tmp12);
	nand2 inst14(tmp10,tmp12,tmp13);
//Y1
	nand2 inst15(tmp9,tmp13,d1);

/*
//first part of Y2
	nand3 inst16(q2,q1bar, InAbar, tmp14);
//second part of Y2
	nand3 inst17(q2bar,q0, InAbar, tmp15);
	nand3 inst18(q2,q0bar, InA, tmp16);
	nand2 inst19(tmp15,tmp16,tmp17);
	nand2 inst20 (q1, tmp17, tmp18);
//Y2
	nand2 inst21(tmp14,tmp18,d2);
*/
	
//first part of Y2
	nor2 inst16(q1bar, q0bar, tmp14);
	nand3 inst17(q2bar, tmp14, InAbar,tmp15);
//second part of Y2
	nand3 inst18(q2, q1bar, InAbar, tmp16);
//thired part of Y2
	xor2 inst19(q0, InAbar, tmp17);
	not1 inst24(tmp17,tmp18);
	nand3 inst20(q2, q1, tmp18,tmp20);
//Y2
	nand3 inst21(tmp15,tmp16,tmp20,d2);

//D flip-flops to store data
	dff dff0(q0,d0,Clk,Reset);
	dff dff1(q1,d1,Clk,Reset);
	dff dff2(q2,d2,Clk,Reset);

//Out
	nand2 inst22(q0, InAbar, tmp19);
	nor3 inst23(q2bar, q1bar, tmp19, Out);

endmodule
